Thomas Chabrier


University Rennes 1-IRISA, Campus ENSSAT, 6 rue Kerampont,
BP80518, 22305 Lannion cedex, France
(+33) (0)2 96 46 92 10


Research Topics

Current Situation

From January 2013, I am member of the ANR ARDyT (Reliable and Reconfigurable Dynamic Architecture) project.

Subject: Arithmetic operators with fault detection/tolerance capabilities.

I am member of the IRISA laboratory and the CAIRN research group.

In collaboration with researchers of the CAIRN team, I work on computation algorithms, representations of numbers and hardware implementations of arithmetic operators with integrated fault detection (and/or fault tolerance) capabilities. The target arithmetic operators are: adders, subtracters, multipliers (and variants of multiplications by constants, square, FMA, MAC), division, square-root, approximations of the elementary functions. We study (and possibly mix) two approaches: residue codes and specific bit-level coding in some redundant number systems for fault detection/tolerance integration at the arithmetic operator/unit level. A complete FPGA prototype will be implemented and strongly tested.

Ph.D. Information

Ph.D. Student in computer science defended on June, 2013.

Title: Arithmetic Recodings for ECC Cryptoprocessors with Protections against Side-Channel Attacks [TeL PDF].

Supervisors: Arnaud Tisserand and Emmanuel Casseau.

Grant: Brittany region and CG22 (Conseil Général 22).

I was member of the IRISA laboratory and the CAIRN research group.

Ph.D. Thesis Abstract

This Ph.D. thesis focused on the study, the hardware design, the theoretical and practical validation, and eventually the comparison of different arithmetic operators for cryptosystems based on elliptic curves (ECC). Provided solutions had to be robust against some side-channel attacks, and efficient at a hardware level (execution speed and area). In the case of ECC, we wanted to protect the secret key, a large integer, used in the scalar multiplication. Our protection methods used representations of numbers, and behaviour of algorithms to make more difficult some attacks. For instance, we randomly changed some representations of manipulated numbers while ensuring that computed values are correct. Redundant representations like signed-digit representation, the double- (DBNS) and multi-base number system (MBNS) have been studied. A proposed method provided an on-the-fly MBNS recoding which operates in parallel to curve-level operations and at very high speed. All recoding techniques have been theoretically validated, simulated extensively in software, and finally implemented in hardware (FPGA and ASIC). A side-channel attack called template attack was also carried out to evaluate the robustness of a cryptosystem using a redundant number representation. Eventually, a study was conducted at the hardware level to provide an ECC cryptosystem with a regular behaviour of computed operations during the scalar multiplication so as to protect against some side-channel attacks.

News and Events


Conferences 2013

Conferences 2012

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Conferences 2010

Teaching in computer science and industrial data processing



Conference articles