Being an ARMs dealer involves taking RISCs

portrait I joined Qualcomm Datacenter Technologies Raleigh in January 2017 to work on future generation ARM microprocessors. Until 2017, I was a research engineer with the PACAP INRIA research team at INRIA Bretagne Atlantique. My research focused on core microarchitecture and in particular, how to increase sequential performance. This included continuing the work I began during my Ph.D., i.e., revisiting a speculation technique that was introduced in the mid 90's: Value Prediction.

Value prediction breaks true data dependencies between instructions and allows to uncover more ILP. Hence, performance is increased by issuing more instructions each cycle. Unfortunately, the research on Value Prediction techniques almost vanished in the early 2000's as it was more effective to increase the number of cores than to dedicate silicon to Value Prediction. However high end processor chips currently feature 8-16 high-end cores and the technology will allow to implement 50-100 of such cores on a single die in a foreseeable future. Amdahl's law suggests that the performance of most workloads will not scale to that level. Therefore, dedicating more silicon area to value prediction in high-end cores might be considered as worthwhile for future multicores.