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Conference articles
2013
  1. K. Bigou, T. Chabrier, and A. Tisserand. Opérateur matériel de tests de divisibilité par des petites constantes sur de très grands entiers. In 15ème Symposium en Architectures nouvelles de machines (SympA), Grenoble, France, January 2013. [PDF]


  2. T. Chabrier and A. Tisserand. On-the-Fly Multi-Base Recoding for ECC Scalar Multiplication without Pre-Computations. In A. Nannarelli, P.-M. Seidel, and P. T. P. Tang, editors, Proc. 21th Symposium on Computer Arithmetic (ARITH), Austin, TX, U.S.A, April 2013. IEEE Computer Society. [PDF]


2012
  1. D. Pamula, E. Hrynkiewicz, and A. Tisserand. Analysis of GF($2^{233}$) Multipliers Regarding Elliptic Curve Cryptosystem Applications. In 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems (PDeS), Brno, Czech Republic, pages 252-257, May 2012.


  2. D. Pamula and A. Tisserand. GF($2^m$) Finite-Field Multipliers with Reduced Activity Variations. In 4th International Workshop on the Arithmetic of Finite Fields, volume 7369 of LNCS, Bochum, Germany, pages 152-167, July 2012. Springer. [PDF] [doi:10.1007/978-3-642-31662-3_11]


  3. A. Tisserand. Circuits for True Random Number Generation with On-Line Quality Monitoring. In 5ème Rencontres Arithmétique de l'Informatique Mathématique (RAIM), June 2012. Note: Invited Talk.


2011
  1. M. Hamilton, W. P. Marnane, and A. Tisserand. A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF($p$) for Specific $p$ Values. In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL), Chania, Greece, pages 273-276, September 2011. IEEE. [PDF] [doi:10.1109/FPL.2011.55]


2010
  1. T. Chabrier, D. Pamula, and A. Tisserand. Hardware Implementation of DBNS Recoding for ECC Processor. In Proc. 44rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 1129-1133, November 2010. IEEE. [PDF] [doi:10.1109/ACSSC.2010.5757580]


  2. D. Pamula, E. Hrynkiewicz, and A. Tisserand. Multiplication in GF($2^m$): area and time dependency/efficiency/complexity analysis. In 10th International IFAC Workshop on Programmable Devices and Embedded Systems (PDeS), Pszczyna, Poland, pages 43-48, October 2010. IFAC.


  3. A. Tisserand. Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC. In Proc. 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Lyon, France, September 2010.


2009
  1. S. Collange, D. Defour, and A. Tisserand. Power Consumption of GPUs from a Software Perspective. In Proc. 9th International Conference on Computational Science (ICCS), volume 5544 of LNCS, Baton Rouge, Louisiana, U.S.A., pages 914-923, May 2009. [PDF] [doi:10.1007/978-3-642-01970-8_92]


  2. P. Giorgi, T. Izard, and A. Tisserand. Comparison of Modular Arithmetic Algorithms on GPUs. In Proc. International Conference on Parallel Computing ParCo, volume 19 of Advances in Parallel Computing, Lyon, France, pages 315-322, September 2009. [doi:10.3233/978-1-60750-530-3-315]


  3. R. Santoro, A. Tisserand, O. Sentieys, and S. Roy. Arithmetic operators for on-the-fly evaluation of TRNGs. In Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVIII, volume 7444, San Diego, California, U.S.A., pages 1-12, August 2009. SPIE. [doi:10.1117/12.826336]


  4. A. Tisserand. Function Approximation based on Estimated Arithmetic Operators. In Proc. 43rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 1798-1802, October 2009. IEEE. [PDF] [doi:10.1109/ACSSC.2009.5470208]


  5. A. Tisserand. Low-Power Arithmetic Operators. In 8èmes journées d'études Faible Tension Faible Consommation, Neuchâtel, Switzerland, June 2009. Note: Invited Talk. [PDF]


  6. A. Tisserand. Opérateurs arithmétiques sécurisés. In 3ème Rencontres Arithmétique de l'Informatique Mathématique (RAIM), October 2009. Note: Invited Talk.


2008
  1. J. Francq, J.-B. Rigaud, P. Manet, A. Tria, and A. Tisserand. Error Detection for Borrow-Save Adders Dedicated to ECC Unit. In 5th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Washington, DC, U.S.A., pages 77-86, August 2008. IEEE. [PDF] [doi:10.1109/FDTC.2008.17]


  2. A. Tisserand. Fast and Accurate Activity Evaluation in Multipliers. In Proc. 42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 757-761, October 2008. IEEE. [PDF] [doi:10.1109/ACSSC.2008.5074510]


2007
  1. A. Byrne, N. Meloni, F. Crowe, W. P. Marnane, A. Tisserand, and E. M. Popovici. SPA Resistant Elliptic Curve Cryptosystem using Addition Chains. In Proc. 4th International Conference on Information Technology (ITNG), Las Vegas, Nevada, U.S.A., pages 995-1000, April 2007. IEEE. [PDF] [doi:10.1109/ITNG.2007.185]


  2. L. Imbert, A. Peirera, and A. Tisserand. A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, volume 6697, San Diego, California, U.S.A., pages 1-9, August 2007. SPIE. [doi:10.1117/12.733652]


  3. A. Tisserand. Estimation rapide de l'activité parasite pour l'optimisation des arbres de réduction de multiplieurs. In 6ème journées d'études Faible Tension Faible Consommation (FTFC), Paris, France, pages 127-130, May 2007.


  4. A. Tisserand. Hardware Reciprocation using Degree-3 Polynomials but Only 1 Complete Multiplication. In Proc. 5th International Northeast Workshop on Circuits & Systems (NEWCAS/MWSCAS), Montréal, Canada, pages 301-304, August 2007. IEEE. [PDF] [doi:10.1109/MWSCAS.2007.4488593]


2006
  1. R. Beguenane, J.-G. Mailloux, S. Simard, and A. Tisserand. Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time. In Proc. Canadian Conference on Electrical and Computer Engineering (CCECE), Ottawa, Canada, pages 908-912, May 2006. IEEE. [PDF] [doi:10.1109/CCECE.2006.277332]


  2. R. Beguenane, S. Simard, and A. Tisserand. Function Evaluation on FPGAs using On-Line Arithmetic Polynomial Approximation. In Proc. 4th International Northeast Workshop on Circuits and Systems (NEWCAS), Gatineau, Canada, pages 21-24, June 2006. IEEE. [PDF] [doi:10.1109/NEWCAS.2006.250959]


  3. R. Glabb, L. Imbert, G. Jullien, A. Tisserand, and N. Veyrat-Charvillon. Multi-mode Operator for SHA-2 Hash Functions. In Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, Nevada, U.S.A., pages 207-210, June 2006. [PDF]


  4. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Carry Prediction and Selection for Truncated Multiplication. In Workshop on Signal Processing Systems (SiPS), Banff, Canada, pages 339-344, October 2006. IEEE. [PDF]


  5. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. New Identities and Transformations for Hardware Power Operators. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVI, volume 6313, San Diego, California, U.S.A., pages 1-10, August 2006. SPIE. [doi:10.1117/12.676244]


  6. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Optimisation d'opérateurs arithmétiques matériels à base d'approximations polynomiales. In 11ème SYMPosium en Architectures nouvelles de machines (SYMPA), Perpignan, France, pages 130-141, October 2006. [PDF]


  7. A. Tisserand. Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials. In Proc. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 2053-2057, October 2006. IEEE. [PDF] [doi:10.1109/ACSSC.2006.355128]


  8. A. Tisserand. Hardware Operator for Simultaneous Sine and Cosine Evaluation. In Proc. International Conference on Acoustics, Speech and Signal Processing (ICASSP), volume 3, Toulouse, France, pages 992-995, May 2006. IEEE. [PDF] [doi:10.1109/ICASSP.2006.1660823]


2005
  1. M. D. Ercegovac, J.-M. Muller, and A. Tisserand. Simple Seed Architectures for Reciprocal and Square Root Reciprocal. In Proc. 39th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 1167-1171, October 2005. IEEE. [PDF]


  2. C.-P. Jeannerod, S.-K. Raina, and A. Tisserand. High-Radix Floating-Point Division Algorithms for Embedded VLIW Integer Processors. In Proc. 17th World Congress on Scientific Computation, Applied Mathematics and Simulation IMACS, Paris, France, July 2005. [PDF]


  3. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Divgen: a divider unit generator. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XV, volume 5910, San Diego, California, U.S.A., pages 1-12, August 2005. SPIE. [doi:10.1117/12.614419]


  4. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Evaluation de polynômes et de fractions rationnelles sur FPGA avec des opérateurs à additions et décalages en grande base. In 10ème SYMPosium en Architectures nouvelles de machines (SYMPA), Le Croisic, France, pages 85-96, April 2005. [PDF]


  5. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Small FPGA polynomial approximations with $3$-bit coefficients and low-precision estimations of the powers of $x$. In S. Vassiliadis, N. Dimopoulos, and S. Rajopadhye, editors, Proc. 16th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Samos, Greece, pages 334-339, July 2005. IEEE Computer Society. Note: Best Paper Award. [PDF]


  6. R. Michard, A. Tisserand, and N. Veyrat-Charvillon. Étude statistique de l'activité de la fonction de sélection dans l'algorithme de E-méthode. In 5ème journées d'études Faible Tension Faible Consommation (FTFC), Paris, France, pages 61-65, May 2005. [PDF]


  7. J.-M. Muller, A. Tisserand, B. Dupont de Dinechin, and C. Monat. Division by Constant for the ST100 DSP Microprocessor. In P. Montuschi and E. Schwarz, editors, Proc. 17th Symposium on Computer Arithmetic (ARITH), Cape Cod, MA., U.S.A, pages 124-130, June 2005. IEEE Computer Society. [PDF]


  8. A. Tisserand. Algorithms and Number Systems for Hardware Computer Arithmetic. In International Symposium on Symbolic and Algebraic Computation (ISSAC), Beijing, China, July 2005. Note: Invited tutorial. [WWW]


2004
  1. C. Bertin, N. Brisebarre, B. Dupont de Dinechin, C.-P. Jeannerod, C. Monat, J.-M. Muller, S. K. Raina, and A. Tisserand. A Floating-Point Library for Integer Processors. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XIV, volume 5559, Denver, Colorado, U.S.A., pages 101-111, August 2004. SPIE. [doi:10.1117/12.557168]


  2. N. Brisebarre, J.-M. Muller, and A. Tisserand. Sparse-Coefficient Polynomial Approximations for Hardware Implementations. In Proc. 38th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., pages 532-535, November 2004. IEEE. [PDF] [doi:10.1109/ACSSC.2004.1399189]


2003
  1. J.-L. Beuchat, L. Imbert, and A. Tisserand. Comparison of Modular Multipliers on FPGAs. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XIII, volume 5205, San Diego, California, U.S.A., pages 490-498, August 2003. SPIE. [doi:10.1117/12.508121]


  2. N. Boullis and A. Tisserand. Some Optimizations of Hardware Multiplication by Constant Matrices. In J.-C. Bajard and M. Schulte, editors, Proc. 16th Symposium on Computer Arithmetic (ARITH), Santiago de Compostela, Spain, pages 20-27, June 2003. IEEE Computer Society. [PDF]


2002
  1. J.-L. Beuchat and A. Tisserand. Opérateur en-ligne sur FPGA pour l'implantation de quelques fonctions élémentaires. In 8ème SYMPosium en Architectures nouvelles de machines (SYMPA), Hamamet, Tunisie, pages 267-274, April 2002. [PDF]


  2. J.-L. Beuchat and A. Tisserand. Small Multiplier-based Multiplication and Division Operators for Virtex-II Devices. In M. Glesner, P. Zipf, and M. Renovell, editors, Proc. 12th International Conference on Field-Programmable Logic and Applications (FPL), volume 2438 of LNCS, Monptellier, France, pages 513-522, September 2002. Springer.


  3. N. Boullis and A. Tisserand. Génération automatique d'architectures de calcul pour des opérations linéaires : application à l'IDCT sur FPGA. In 8ème SYMPosium en Architectures nouvelles de machines (SYMPA), Hamamet, Tunisie, pages 283-290, April 2002. [PDF]


2001
  1. N. Boullis and A. Tisserand. On Digit-Recurrence Division Algorithms for Self-Timed Circuits. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architecture and Implementations XI, volume 4474, San Diego, California, U.S.A., pages 115-125, August 2001. SPIE. [doi:10.1117/12.448640]


  2. F. de Dinechin and A. Tisserand. Some Improvements on Multipartite Tables Methods. In N. Burgess and L. Ciminiera, editors, Proc. 15th Symposium on Computer Arithmetic (ARITH), Vail, Colorado, U.S.A., pages 128-135, June 2001. IEEE Computer Society. [PDF]


2000
  1. F. de Dinechin and A. Tisserand. Table-Based Methods Comparison for Low-Precision Evaluation of the Sine and Cosine Functions on FPGAs. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures, and Implementations X, volume 4116, San Diego, California, U.S.A., pages 226-234, August 2000. SPIE. [doi:10.1117/12.406500]


1999
  1. B. Girau, P. Marchal, P. Nussbaum, A. Tisserand, and H. F. Restrepo. A Massively Parallel One-Chip Architecture: Towards Evolvable Array Processing. In Proc. International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro), Granada, Spain, pages 187-193, April 1999. IEEE. [PDF]


  2. A. Tisserand, P. Marchal, and C. Piguet. An On-Line Arithmetic based FPGA for Low-Power Custom Computing. In Proc. 9th International Workshop on Field Programmable Logic and Applications (FPL), volume 1673 of LNCS, London, England, pages 264-273, September 1999. Springer. [PDF]


  3. A. Tisserand, P. Marchal, and C. Piguet. FPOP: Field Programmable On-line oPerators. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures and Implementations IX, volume 3807, Denver, Colorado, U.S.A., pages 31-42, September 1999. SPIE. [doi:10.1117/12.367658]


1998
  1. M. D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand. Reciprocation, Square Root, Inverse Square Root, and some Elementary Functions using Small Multipliers. In F. T. Luk, editor, Proc. Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, volume 3461, San Diego, California, U.S.A., pages 543-554, June 1998. SPIE. [doi:10.1117/12.325713]


  2. F. Kaess, R. Kanan, M. Declercq, A. Tisserand, J.-M. Muller, B. Hochet, and J.-M. Vincent. A Fast Encoding Architecture for High-Speed Flash Analog-to-Digital Converters. In Proc. 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Szczyrk, Poland, pages 237-243, September 1998. IEEE.


  3. F. Kaess, R. Kanan, M. Declercq, A. Tisserand, J.-M. Muller, B. Hochet, and J.-M. Vincent. Improving High-Speed Flash Analog-to-Digital Converters Accuracy using Sum Encoding. In Proc. International Symposium On Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Budapest, Hungary, September 1998.


  4. P. Nussbaum, B. Girau, and A. Tisserand. Field Programmable Processor Arrays. In M. Shipper, D. Mange, and A. Perez-Uribe, editors, Proc. 2nd International Conference on Evolvable Systems (ICES): from biology to hardware, volume 1478 of LNCS, Lausanne, Switzerland, pages 311-322, September 1998. Springer.


1997
  1. M. Daumas, J.-M. Muller, and A. Tisserand. Very High Radix On-Line Arithmetic for Accurate Computations. In Proc. 15th World Congress on Scientific Computation, Modelling and Applied Mathematics (IMACS), Berlin, Germany, August 1997.


  2. V. Lefèvre, J.-M. Muller, and A. Tisserand. Towards Correctly Rounded Transcendental. In T. Lang, J.-M. Muller, and N. Takagi, editors, Proc. 13th Symposium on Computer Arithmetic (ARITH), Asilomar, California, U.S.A., pages 132-137, July 1997. IEEE Computer Society. [PDF]


  3. J.-M. Muller, A. Tisserand, and J.-M. Vincent. Asynchronous Sub-Logarithmic Adders. In Proc. Pacific Rim Conference on Communication, Computers and Signal Processing (PACRIM), volume 2, Victoria, Canada, pages 515-518, August 1997. IEEE. [PDF]


  4. A. Tisserand and M. Dimmler. FPGA Implementation of Real-Time Digital Controllers using On-Line Arithmetic. In Proc. 7th International Workshop on Field Programmable Logic and Applications (FPL), volume LNCS-1304, London, England, pages 472-481, August 1997. Springer.


1996
  1. M. Daumas, J.-M. Muller, and A. Tisserand. Theoretical Support for Standardized Elementary Functions. In Proc. International Symposium on Modelling, Analysis and Simulation (IMACS), volume 2, Lille, France, pages 1133-1138, July 1996. IEEE-SMC.


  2. B. Girau and A. Tisserand. On-Line Arithmetic based Reprogrammable Hardware Implementation of Multilayer Perceptron Back-Propagation. In Proc. 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro), Lausanne, Switzerland, pages 168-175, February 1996. IEEE Computer Society. [PDF]


  3. A. Tisserand. FPGA Implementation of On-Line Arithmetic Operators for Digital Control. In Proc. International Workshop on Logic and Architecture Synthesis (IWLAS), Grenoble, France, pages 115-122, December 1996.


1995
  1. M. D. Ercegovac, J.-M. Muller, and A. Tisserand. FPGA Implementation of Polynomial Evaluation Algorithm. In J. Schewel, editor, Proc. Field Programmable Gate Arrays for Fast Board Development and Reconfigurable Computing, volume 2607, Philadelphia, Pennsylvania, U.S.A., pages 177-188, October 1995. SPIE. [doi:10.1117/12.221338]


  2. J.-M. Muller, A. Scherbyna, and A. Tisserand. Semi-Logarithmic Number Systems. In S. Knowles and W. H. McAllister, editors, Proc. 12th Symposium on Computer Arithmetic (ARITH), Bath, England, pages 201-207, July 1995. IEEE Computer Society. [PDF]


  3. J.-M. Muller and A. Tisserand. Towards Exact Rounding of the Elementary Functions. In Proc. International Symposium On Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), volume 90, Wuppertal, Germany, pages 59-71, September 1995.


1994
  1. A. Tisserand. Etude d'un Produit Scalaire Haute Précision sur Mémoire Active Programmable. In Journées Jeunes Chercheurs en Architectures de Machines et Systèmes, Monastir, Tunisie, pages 211-220, December 1994. PRC ANM, Réseau Doctoral en Architecture de Machines et Systèmes.



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